Sony announces its first ever 3-Layer stacked CMOS image sensor with DRAM for smartphones

Sony, the Japanese multinational conglomerate has just announced its first 3-layered stacked CMOS sensor with DRAM for smartphones. While it is the first from Sony, the new sensor has been developed with an aim to drastically improve mobile photography for the smartphones.

As for the sensor itself, Sony claims that the new image sensor consists of a DRAM layer added to the conventional 2-layer stacked CMOS image sensor with a layer of back-illuminated structure pixels and a chip affixed with mounted circuits for signal processing.

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Hence, this newly developed sensor with DRAM is expected to deliver fast data readout speeds, making it possible for you to capture still images of fast-moving subjects with minimal focal plane distortion as well as super slow motion movies at up to 1,000 frames per second (approximately 8x faster than conventional products) in full HD (1920x1080 pixels).

Explaining on how the sensor achieves such speed, Sony says, "In order to realize the high-speed readout, the circuit used to convert the analog video signal from pixels to a digital signal has been doubled from a 2-tier construction to a 4-tier construction in order to improve processing ability. Although there are speed limitations in the interface specifications for outputting signals from image sensors to other LSIs, this sensor uses DRAM to store signals read at high speed temporarily, enabling data to be output at an optimal speed for the standard specifications." "As a result, the product is capable of reading one still image of 19.3 million pixels in only 1/120 of a second (approximately 4x faster than conventional products), thereby supporting high-speed image capture."

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Well, hopefully, this will be a game changer product for the photography department from Sony. It has indeed used most of its expertise in stacked image sensor manufacturing technology to develop this new product. Sony has ensured that quality and reliability will remain high despite the complex three-layered construction.

These development results were announced at the International Solid-State Circuits Conference (ISSCC) which started on Sunday, February 5, 2017, in San Francisco.