Intel ARC GPU To Work With AMD GPUs With Support For XeSS Super Sampling Technology


Intel recently showcased the next-generation of CPUs and the first set of dedicated GPUs under its ARC branding. The company showcased various features and specifications of the upcoming chipsets during Intel Architecture Day 2021.

Intel ARC GPU To Work With AMD GPUs With Support For XeSS

Soon after the Intel Architecture Day 2021, we had some queries related to the upcoming Intel products. Roshni Das, Director - Marketing Intel India has answered some of our queries, and here are her responses, which will help you understand the upcoming products from Intel.

Is the Alchemist GPU cross-compatible with AMD CPU?

Yes. In fact, if you look at the way we've implemented XeSS, our method of Super Sampling, even that will work on competition hardware.

Is Intel making any special adjustments to make ARC a non-mining GPU?

Xe HPG was designed as gaming first microarchitecture, and our priority is to support gamers.

Intel ARC GPU To Work With AMD GPUs With Support For XeSS

How different are Alder Lake P and E cores in comparison to Willow Cove and Sunny Cove cores?

From Skylake architecture (Comet Lake) to the Cypress Cove architecture (Rocket Lake), we showcased a 19% ISO frequency improvement. Now with Performance-core (Alder Lake), we are demonstrating a further 19% ISO frequency improvement over the Cypress Cove architecture (Rocket Lake).

We expect the mobile curve comparison of Performance-core (Alder Lake) to Willow Cove (Tiger Lake) to show similar ISO frequencies improvements as the desktop cure that we showed at Architecture Day.

How efficient will be angstrom CPUs when compared to Tiger Lake or Alder Lake and when can we expect them to hit the market?

Intel 20A will be a watershed moment in process technology when we introduce it in the first half of 2024 and will feature two new breakthrough technologies - RibbonFET, our first new transistor architecture since we pioneered FinFETs in 2011, and a first of its kind innovation for backside power delivery called PowerVia.


Will all Alder Lake CPUs (desktops, H35, and U) will be based on Intel 7 fabrication?

Yes. Alder Lake will be Intel's first processor built on the Intel 7 process and will serve as the foundation for leadership desktop and mobile processors that deliver smarter, faster, and more efficient real-world computing. Alder Lake features a multi-core architecture that mixes Performance cores and Efficient cores for high performance and high efficiency.

It will leverage faster transistors and an improved MIM capacitor. Compared to the Willow Cove cores found in 11th Gen Intel Core processors, Performance cores provide Alder Lake with improved security features and increased single-threaded performance.

What Is Intel Thread Director?

Intel Thread Director is Intel's unique approach to scheduling developed to ensure Efficient cores and Performance cores work seamlessly together, dynamically and intelligently assign workloads from the start, and optimizing the system for maximum real-world performance and efficiency. Intelligence built directly into the core - works seamlessly with the operating system to place the right thread on the right core at the right time.

Intel's high-performance hybrid approach is further enhanced by Intel Thread Director. The technology is designed into Alder Lake and helps the operating system make more intelligent and informed decisions about where to place running threads. Thread Director is fundamental to unleashing the potential for performance hybrid. It is fully dynamic, adaptive, and autonomous vs. a static, deterministic, software-only approach.

Key features of Sapphire Rapids and its SoC architecture

Combining Intel's performance cores with new accelerator engines, Sapphire Rapids sets the standard for next-generation data center processors. Sapphire Rapids is Intel's next-generation Xeon Scalable Processor built on Intel 7 process technology and featuring the new performance x86 core. At the heart of Sapphire Rapids is a tiled, modular SoC architecture that delivers significant scalability while still maintaining the benefits of a monolithic CPU interface thanks to Intel's EMIB packaging technology.

Sapphire Rapids delivers substantial compute performance across traditional datacenter usages with unique purpose-built optimizations for performance on elastic compute models like cloud microservices and AI. Sapphire Rapids uses the new performance core, increases core counts over the prior generation, and delivers the industry's broadest range of datacenter-relevant accelerators, including Intel Advanced Matrix Extensions (AMX), Intel Data Streaming Accelerator (DSA), and Intel Accelerator Interfacing Architecture (AiA) that enable great performance at datacenter scale.

The advanced Intel platform is designed to deliver a balanced architecture featuring industry-leading DDR5 memory, CXL 1.1, PCIe 5.0, and HBM technologies to deliver high throughput, low latency performance.

There are additional technologies and features around power management, security & RAS, as well as further optimizations and targeted new instructions that will be revealed closer to product launch.

What are Infrastructure Processing Unit (IPU) and its advantages?

An IPU is an advanced networking device with hardened accelerators and Ethernet connectivity that accelerates and manages infrastructure functions using tightly coupled, dedicated, programmable cores. An IPU offers full infrastructure offload and provides an extra layer of security by serving as a control point of the host for running infrastructure applications.

An IPU processes infrastructure functions. IPU's are used to accelerate infrastructure functions like network virtualization, storage virtualization, security isolation, and providing root-of-trust. We believe that the Infrastructure Processing Unit better captures the essence of these functions.

What are Mount Evans and Oak Springs Canyon; and a SmartNIC - Arrow Creek?

Recognizing "one-size-does-not-fit-all," Intel at Architecture Day 2021, offered a deeper look at its IPU architecture and introduced two new members of the IPU family and a SmartNIC - all designed to address the complexity of diverse and dispersed data centers.

Mount Evans is Intel's first ASIC IPU. It has been architected and developed hand-in-hand with a top cloud service provider. Hyperscale ready, Mount Evans integrates learnings from multiple generations of FPGA SmartNICs and offers high-performance network and storage virtualization offload while maintaining a high degree of control.

Mount Evans also provides a best-in-class programmable packet processing engine enabling known use cases like firewalls and virtual routing. In addition, Mount Evans implements a hardware-accelerated NVMe storage interface scaled up from Intel Optane technology to emulate NVMe devices. Incorporating security from the ground up, Mount Evans deploys advanced crypto and compression acceleration leveraging Intel's high-performance Quick Assist technology.

Finally, Mount Evans can be programmed using existing, commonly deployed software environments including DPDK, SPDK, and the pipeline can be configured utilizing the P4 programming language pioneered by Intel's Barefoot Switch Division. Mount Evans maximizes performance and efficiency because it is a dedicated ASIC. We will publicly share product availability in the future.

Oak Springs Canyon is an IPU reference platform built with Intel Xeon-D and Agilex FPGA, the industry's leading FPGA in power, efficiency, and performance. The Oak Springs Canyon FPGA-based IPU offloads network virtualization functions like Open Virtual Switch (OVS) and storage functions like NVMe over Fabric, RoCE v2 and it provides a hardened crypto block providing a more secure, high speed 2x 100Gb Ethernet connectivity. In addition, the Intel Open FPGA Stack is a scalable, source-accessible software and hardware infrastructure that enables our partners and customers to customize their solutions.

Oak Springs Canyon can also be programmed using existing, commonly deployed software environments including DPDK and SPDK which have been optimized on x86. This reference platform is built with Intel Xeon-D and Agilex FPGA, which is the industry's leading FPGA in power, efficiency, and performance. The Agilex FPGA on Oak Springs Canyon enables solution partners and customers to adapt quickly implementing new or proprietary protocols offloaded from the host.

Intel N6000 Acceleration Development Platform (code-named Arrow Creek): The Intel N6000 Acceleration Development Platform, code-named Arrow Creek, is a SmartNIC designed for use with Xeon-based servers. It can flexibly accelerate several infrastructure workloads like Juniper Contrail, OVS, and SRv6.

Designed for use with Xeon-based servers, this Acceleration Development Platform (ADP) features Intel's Agilex FPGA, which is the industry's leader in power, efficiency, and performance, and the Intel Ethernet 800 Series Controller for high performance 100G connectivity. The Agilex FPGA provides hardware flexibility, enabling customers to add functionality when needed or implement new or proprietary protocols to accelerate host-based infrastructure functions.

Intel ADPs are platforms designed by Intel that enable the development of FPGA-based acceleration solutions. ADPs are foundational building blocks used by ODMs and solutions partners to design, test, and validate their solutions for cloud and comms customers. Commercial versions of ADPs are brought to market by Intel partners, customers, or Intel.

What is Ponte Vecchio and how important is this for the future of computing?

Ponte Vecchio SoC is Intel's first product based on the Xe HPC architecture. It is composed of several complex designs, that manifest in 47 tiles, using 5 different process nodes both internal and external. It uses advanced packaging technology to deliver industry-leading FLOPs and compute density to accelerate AI, HPC, and advanced analytics workloads.

The new Xe HPC microarchitecture is built for scalability and is designed to take advantage of the most advanced silicon technologies, built using 5 different process nodes. It is a great example of Intel's ability to combine multiple process technologies - both internal and external - with advanced packaging technologies to uniquely tailor products to customer and market needs. Ponte Vecchio is easily accessible to developers through Intel's oneAPI toolkit.

The oneAPI industry initiative is an open, standards-based, unified software stack that is cross-architecture and cross-vendor and delivers a seamless way to take advantage of GPU-based acceleration. Ponte Vecchio will be released in 2022 for HPC and AI markets.

Ponte Vecchio is an excellent demonstration of Intel's ability to combine multiple process technologies, both internal and external with novel packaging technologies to uniquely tailor products to customer and market needs.

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